The present invention relates to a mechanism for managing the translation look-aside buffer (TLB) of an emulated machine.
Computers comprise a processor or central processing unit (CPU) that carries out the instructions of a computer program and is the primary element performing the function of the computer CPUs are generally associated with memory, commonly in the form of random access memory (RAM), for storing data used in the processing of the instruction by the CPU. The RAM may be addressed using virtual addressing, with the translation between virtual and real addresses commonly being managed by a memory management unit (MMU) associated with the CPU. A page table is maintained by the MMU, which comprises the translations of the virtual address space to the corresponding physical address space.
A virtual address space may be very large and searching it for a given translation may be computationally expensive or time consuming. Thus, in order to speed up virtual address translation, the MMU is arranged to maintain a specialised cache in the form of a translation look-aside buffer (TLB). The TLB is used to hold a set of entries comprising the most recently used translations between the virtual address space and the physical address space. A TLB is commonly implemented as content addressable memory (CAM). Thus, the CAM search key is a virtual address and the search result is the corresponding physical address. If the TLB is searched and the given virtual address cannot be found, the MMU proceeds to locate the virtual address in the page table. Once located, and the translation returned to the MMU, the located virtual to physical address mapping is entered in the TLB.
A problem arises when a computer is emulated, for example, where the function of a given computer or machine is synthesised by a software system. In an emulated CPU, the computational cost of a virtual address translation is commonly proportionally higher than on a non-emulated CPU. Furthermore, if changes are made in the emulated hardware, some operating systems that are designed to run on the relevant CPU may no longer run as expected or processing errors may result.